info_vmepatch_ohl - CIEMAT Particle Physics
The VMEPATCH board was designed to expand the VME bus protocol from a 3U backplane into a custom J2 backplane (J2_OFCU). It supports short non-privileged A16 D16 (Word) VME access and translates to the J2 boards (OFCU or TSC_rear boards) by means of a custom parallel protocol.
J2_OFCU contains 4 address lines and 8 bits of data. The communication protocol is parallel and works with one READ/WRITE line, one board select line for each of the 12 available J2 slots and it also includes a reset line.
This communication protocol used by VME-PATCH consists of the following basic principle:
VME-PATCH board receives 16 address lines from the VME backplane.
- Bits 15 to 10 (VME-PATCH base address) allow identify the VME-PATCH board that is being accessed. A switch included on every VME-PATCH lets them select a unique base address. The VME-PATCH board will only respond to a R/W access if the value of those bits corresponds to its base address.
- Bits 9 to 6 (OFCu base address) identify which OFCu is being accessed. According to the value of these bits, the VME-PATCH board actives the correct Board_sel signal allowing that OFCu board to respond to the R/W access. If all the bits take the value 0, the acces to the VME-PATCH is required.
- Bits 5 to 1 (registry address) identify the registry of the VME-PATCH or OFCu boards to be accessed. Because of the fact that there are no more than 16 registers, only four bits are needed to code them, so bit 5 is not currently used.
- Bit 0 is used to address every byte in the VME protocol mode D16.
- VMEPATCH Technical Report
- VMEPATCH image
- VMEPATCH schematics
- VMEPATCH list of material
- VMEPATCH Gerber files